1. Field of the Invention
The present invention relates to information storage systems and, in particular, to a method for late programming of MOS integrated circuit devices.
2. Discussion of the Art
The principal modern method for fabricating semiconductor integrated circuits is the so-called planar process. The planar process relies on the unique characteristics of silicon and comprises a complex sequence of manufacturing steps involving deposition, oxidation, photolithography, diffusion and/or ion implantation, and metallization, to fabricate a "layered" integrated circuit device in a silicon substrate.
For example, oxidation of a crystalline silicon substrate results in the formation of a layer of silicon dioxide on the substrate surface. Photolithography can then be used to selectively pattern and etch the silicon dioxide layer to expose a portion of the underlying substrate. These openings in the silicon dioxide layer allow for the introduction ("doping") of ions ("dopant") into defined areas of the underlying silicon. The silicon dioxide acts as a mask; that is, doping only occurs where there are openings. Careful control of the doping process and of the type of dopant allows for the creation of localized areas of different electrical resistivity in the silicon. The particular placement of acceptor ion-doped (positive free hole, "p") regions and donor ion-doped (negative free electron, "n") regions in large part defines the interrelated design of the transistors, resistors, capacitors and other circuit elements on the silicon wafer. Electrical interconnection and contact to the various p or n regions that make up the integrated circuit is made by a deposition of a thin film of conductive material, usually aluminum or polysilicon, thereby finalizing the design of the integrated circuit.
Of course, the particular fabrication process and sequence used will depend on the desired characteristics of the semiconductor device. Today, one can choose from among a wide variety of devices and circuits to implement a desired digital or analog logic feature.
Where it is desired to have semiconductor devices with uncommitted logic gates such that the final logic configuration of the device is determined by the end user, the fabrication process must allow for programming of the device. Programming normally involves adjusting threshold voltages of particular gate transistors located either in or out of a memory row and column matrix. If the memory matrix is formed utilizing MOS depletion type transistors, then programming involves reduction of the threshold voltage of selected transistors to below a predetermined operating voltage level for the matrix. Threshold reduction is achieved by doping the region of the selected depletion devices utilizing ions of a conductivity type the same as that of the MOS transistor's source and drain. If on the other hand, the memory matrix is formed utilizing enhancement type MOS transistors, then programming selectively raises, not reduces, the threshold voltage of the selected transistors above a predetermined operating voltage level for the matrix. Threshold increases are achieved by introducing into the channel region ions of a conductivity type opposite to that of the MOS transistor's source and drain.
Because later steps in the fabrication process can affect characteristics introduced in earlier steps in the process, logic programming is most commonly and easily achieved during an early wafer processing step. Early programming generally presents no design inconveniences for the bulk manufacturing of standard semiconductor devices. On the other hand, where it is desired to produce more unique or "customized" devices, early programming results in unacceptably long fabrication cycle time from the programming step to the shipment date. For faster turnaround, there is a need to program as late in the fabrication sequence as possible, so that few, if any, steps separate the unprogrammed chip from shipment.
Attempts have been made to provide for programming of logic later in the fabrication cycle. Uniformly, such late programming methods utilize ion implantation to adjust the channel voltage thresholds. In general, the variations among these late programming methods involve the number of layers through which ion implantation is performed. In one case, for example, very high energy ion implantation is performed to penetrate many layers and great thickness of materials. In another case, low energy ion implantation is performed after etching a deep hole in the deposited layers.
There are a number of problems with the ion implantation approach to late programming. Most importantly, there is the problem of metallization over the region to be doped. Metallization will block and prevent proper ion implantation. Furthermore, even if metallization can be avoided in the physical area of ion implant, achieving doping at the required depth requires an ion implantation instrument with very high ion beam energy (approximately 1 MEV), high dose (approximately 10.sup.14 cm.sup.-2) and high throughput capacity. Ion implant equipment required to meet these requirements is extremely expensive and not production proven.
The approach of etching a deep hole down through the successive device layers would allow, of course, for the use of an ion implantation instrument of lower ion beam energy (approximately 360 KEV). Unfortunately, this solution is not practical. First, the cutting must avoid all other metallization (lateral error). Second, the cutting must stop precisely before the region to be doped (vertical error). Thirdly, metallization cannot be routed over the region after doping without further passivation.
Therefore, it would be highly desirable to have available a method for programming integrated circuits without the need for expensive and specialized equipment. Furthermore, it would be highly desirable to have available a method for programming integrated circuits after metallization.